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RMPA1967 US-PCS CDMA, CDMA2000-1X and WDCMA Power EdgeTM Power Amplifier Module
February 2005
RMPA1967 US-PCS CDMA, CDMA2000-1X and WDCMA Power EdgeTM Power Amplifier Module
Features
Single positive-supply operation and low power and shutdown modes 40% CDMA/WCDMA efficiency at +28 dBm average output power Compact lead-free compliant, LCC package(3.0 x 3.0 x 1.0 mm nominal) Internally matched to 50 ohms and DC blocked RF input/output Meets CDMA2000-1XRTT/WCDMA performance requirements Alternative pin-out to Fairchild RMPA1965
General Description
The RMPA1967 power amplifier module (PAM) is designed for CDMA, CDMA2000-1X and WCDMA personal communications system (PCS) applications. The 2-stage PAM is internally matched to 50 Ohms to minimize the use of external components and features a low-power mode to reduce standby current and DC power consumption during peak phone usage. High power-added efficiency and excellent linearity are achieved using Fairchild RF's InGaP Heterojunction Bipolar Transistor (HBT) process.
Device
Functional Block Diagram
(Top View)
MMIC Vref 1 DC Bias Control Vmode 2 Input Match Output Match 7 GND 8 GND
RF IN
3
6
RF OUT
Vcc1
4
5
Vcc2
(paddle ground on package bottom)
(c)2005 Fairchild Semiconductor Corporation
1
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RMPA1967 Rev. C
RMPA1967 US-PCS CDMA, CDMA2000-1X and WDCMA Power EdgeTM Power Amplifier Module
Absolute Ratings1
Parameter
Supply Voltages Reference Voltage Power Control Voltage RF Input Power Storage Temperature
Symbol
Vcc1, Vcc2 Vref Vmode Pin Tstg
Value
5.0 2.6 to 3.5 3.5 +10 -55 to +150
Units
V V V dBm C
Note: 1. No permanent damage with one parameter set at extreme limit. Other parameters set to typical values.
Electrical Characteristics1
Parameter
Operating Frequency C CDMA Operation Small-Signal Gain Power Gain SSg Gp 26 27 24 Linear Output Power Po 28 16 PAEd (digital) @ +28 dBm PAEd (digital) @ +16 dBm PAEd (digital) @ +16 dBm High Power Total Current Low Power Total Current Adjacent Channel Power Ratio 1.25 MHz Offset ACPR1 -50 -52 2.25 MHz Offset ACPR2 -60 -68 General Characteristics Input Impedance Noise Figure Receive Band Noise Power Harmonic Suppression Spurious Outputs2,3 Ruggedness w/ Load Mismatch3 Tc -30 VSWR NF Rx No 2fo-5fo S 2.0:1 4 -139 -50 -60 10:1 85 C dB dBm/Hz dBc dBc Po +28 dBm; 1930 to 1990 MHz Po < +28 dBm Load VSWR 5.0:1 No permanent damage. dBc dBc dBc dBc Itot PAEd 40 10 25 460 120 dB dB dB dBm dBm % % % mA mA Po = 0 dBm Po = +28 dBm; Vmode = 0V Po = +16 dBm; Vmode > 2.0V Vmode = 0V Vmode > 2.0V Vmode = 0V Vmode > 2.0V Vmode 2.0V, Vcc = 1.4 V Po = +28 dBm, Vmode = 0V Po = +16 dBm, Vmode = 2.0V IS-95 Po = +28 dBm; Vmode = 0V Po = +16 dBm; Vmode = 2.0V Po = +28 dBm; Vmode = 0V Po = +16 dBm; Vmode = 2.0V
Symbol Min
f 1850
Typ
Max
1910
Units
MHz
Comments
Case Operating Temperature DC Characteristics Quiescent Current Reference Current Shutdown Leakage Current
Iccq Iref Icc(off)
45 5 1 5
mA mA A
Vmode > 2.0V Po +28 dBm No applied RF signal.
Notes: 1. All parameters met at Tc = +25C, Vcc = +3.4V, Vref = 2.85V, f = 1880 MHz and load VSWR 1.2:1, unless otherwise noted. 2. All phase angles. 3. Guaranteed by design.
2 RMPA1967 Rev. C
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RMPA1967 US-PCS CDMA, CDMA2000-1X and WDCMA Power EdgeTM Power Amplifier Module
Performance Data
RMPA1967 US PCS 3x3mm2 PAM Vcc=3.4V, Vref = 2.85V, Vmode=0V, Pout=28dBm
30.0 29.0 28.0 27.0 -30C +25C +85C
RMPA1967 US PCS 3x3mm2 PAM Vcc=3.4V, Vref = 2.85V, Vmode=0V, Pout=28dBm
45.0 44.0 43.0 42.0 -30C +25C +85C
Gain (dB)
PAE (%)
26.0 25.0 24.0 23.0 22.0 21.0 20.0 1850 1880
41.0 40.0 39.0 38.0 37.0 36.0 35.0
1910
1850
1880
1910
Frequency (MHz)
Frequency (MHz)
RMPA1967 US PCS 3x3mm2 PAM Vcc=3.4V, Vref = 2.85V, Vmode=0V, Pout=28dBm
500.0 490.0 480.0 470.0 -40.0 -42.0 -44.0 -46.0 -48.0 -50.0 -52.0 -54.0 -56.0 -58.0 1880 1910
RMPA1967 US PCS 3x3mm2 PAM Vcc=3.4V, Vref = 2.85V, Vmode=0V, Pout=28dBm
Icc (mA)
460.0 450.0 440.0 430.0 420.0 410.0 400.0 1850
+25C -30C
ACPR1 (dBc)
+85C
+85C +25C -30C
-60.0 1850
1880
1910
Frequency (MHz)
Frequency (MHz)
RMPA1967 US PCS 3x3mm2 PAM Vcc=3.4V, Vref = 2.85V, Vmode=0V, Pout=28dBm
-50.0 -52.0 -54.0 -56.0 -58.0 -60.0 -62.0 -64.0 -66.0 -68.0 -70.0 1850 1880 1910 -30C +25C +85C
ACPR2 (dBc)
Frequency (MHz)
3 RMPA1967 Rev. C
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RMPA1967 US-PCS CDMA, CDMA2000-1X and WDCMA Power EdgeTM Power Amplifier Module
Efficiency Improvement Applications
In addition to high-power/low-power bias modes, the efficiency of the PA module can be significantly increased at backed-off RF power levels by dynamically varying the supply voltage (Vcc) applied to the amplifier. Since mobile handsets and power amplifiers frequently operate at 10-20 dB back-off, or more, from maximum rated linear power, battery life is highly dependent on the DC power consumed at antenna power levels in the range of 0 to +16dBm. The reduced demand on transmitted RF power allows the PA supply voltage to be reduced for improved efficiency, while still meeting linearity requirements for CDMA modulation with excellent margin. High-efficiency DC-DC converters are now available to implement switched-voltage operation. With the PA module in low-power mode (Vmode = +2.0V) at+16dBm output power and supply voltages reduced from 3.4V nominal down to 1.2V, power-added efficiency is more than doubled from 9.5 percent to nearly 25 percent (Vcc = 1.2V) while maintaining a typical ACPR1 of -52dBc and ACPR2 of less than -61dBc. Operation at even lower levels of Vcc supply voltage are possible with a further restriction on the maximum RF output power.
Recommended Operating Conditions
Parameter
Operating Frequency Supply Voltage Reference Voltage (operating) (shutdown) Bias Control Voltage (low-power) (high-power) Linear Output Power (high-power) (low-power) Case Operating Temperature Tc -30 Pout Vmode
Symbol
f Vcc1, Vcc2 Vref
Min
1850 3.0 2.7 0 1.8 0
Typical
3.4 2.85
Max
1910 4.2 3.1 0.5
Units
MHz V V V V V dBm dBm C
2.0
3.0 0.5 +28 +16 +85
DC Turn-On Sequence
1) Vcc1 = Vcc2 = 3.4V (typical) 2) Vref = 2.85V (typical) 3) High-Power: Vmode = 0V (Pout > 16 dBm) Low-Power: Vmode = 2V (Pout < 16 dBm)
4 RMPA1967 Rev. C
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RMPA1967 US-PCS CDMA, CDMA2000-1X and WDCMA Power EdgeTM Power Amplifier Module
Evaluation Board Layout
5 1 4 2 7
XYTT 1967
Z
5 5 6 6 3
Materials
Qty
1 2 7 Ref 3 3 2 1 1 A/R A/R
Item No.
1 2 3 4 5 5 (Alt) 6 7 7 (Alt) 8 9
Part Number
G658001-1 V1 #142-0701-841 #2340-5211TN GRM39X7R102K50V ECJ-1VB1H102K C3216X5R1A335M GRM39Y5V104Z16V ECJ-1VB1C104K SN63 SN96 PC Board
Description
SMA Connector Terminals Assembly, RMPA1967 1000pF Capacitor (0603) 1000pF Capacitor (0603) 3.3F Capacitor (1206) 0.1F Capacitor (0603) 0.1F Capacitor (0603) Solder Paste Solder Paste
Vendor
Fairchild Johnson 3M Fairchild Murata Panasonic TDK Murata Panasonic Indium Corp. Indium Corp.
Evaluation Board Schematic
0.1 F 1000 pF Vmode SMA1 RF IN 50 Ohm TRL Vcc1 3.3 F 1000 pF 1000pF (package base) 9 Vref 1 2 3 4 8
Z
XYTT 1967
7 6 5 50 Ohm TRL Vcc2 3.3 F SMA2 RF OUT
5 RMPA1967 Rev. C
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RMPA1967 US-PCS CDMA, CDMA2000-1X and WDCMA Power EdgeTM Power Amplifier Module
Package Outline
I/O 1 INDICATOR 1 2 3.00+.100 mm SQ. -.050 3 4 TOP VIEW 8
Z XYTT 1967
FRONT VIEW
7
6 5
X Z 19 YTT 67
1.10mm MAX.
4X R.20mm 4 BACK SIDE SOLDER MASK 3 6 2.65mm 2 9 1.40mm BOTTOM VIEW 7 8 0.175mm 0.40mm 0.10mm 1 0.40mm 0.10mm DETAIL A TYP. 5 2 0.40mm
SEE DETAIL A 0.80mm
1
Signal Descriptions
Pin #
1 2 3 4 5 6 7 8
Signal Name
Vref Vmode RF In Vcc1 Vcc2 RF Out GND GND Reference Voltage
Description
High-Power/Low-Power Mode Control RF Input Signal Supply Voltage to Input Stage Supply Voltage to Output Stage RF Output Signal Ground Ground
6 RMPA1967 Rev. C
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RMPA1967 US-PCS CDMA, CDMA2000-1X and WDCMA Power EdgeTM Power Amplifier Module
Application Information
Precautions to Avoid Permanent Device Damage: * Cleanliness: Observe proper handling procedures to ensure clean devices and PCBs. Devices should remain in their original packaging until component placement to ensure no contamination or damage to RF, DC & ground contact areas. * Device Cleaning: Standard board cleaning techniques should not present device problems provided that the boards are properly dried to remove solvents or water residues. * Static Sensitivity: Follow ESD precautions to protect against ESD damage: - A properly grounded static-dissipative surface on which to place devices. - Static-dissipative floor or mat. - A properly grounded conductive wrist strap for each person to wear while handling devices. * General Handling: Handle the package on the top with a vacuum collet or along the edges with a sharp pair of bent tweezers. Avoiding damaging the RF, DC, & ground contacts on the package bottom. Do not apply excessive pressure to the top of the lid. * Device Storage: Devices are supplied in heat-sealed, moisture-barrier bags. In this condition, devices are protected and require no special storage conditions. Once the sealed bag has been opened, devices should be stored in a dry nitrogen environment. * Device Usage: Fairchild recommends the following procedures prior to assembly. - Dry-bake devices at 125C for 24 hours minimum. Note: The shipping trays cannot withstand 125C baking temperature. - Assemble the dry-baked devices within 7 days of removal from the oven. - During the 7-day period, the devices must be stored in an environment of less than 60% relative humidity and a maximum temperature of 30C - If the 7-day period or the environmental conditions have been exceeded, then the dry-bake procedure must be repeated. Solder Materials & Temperature Profile: Reflow soldering is the preferred method of SMT attachment. Hand soldering is not recommended. * Reflow Profile - Ramp-up: During this stage the solvents are evaporated from the solder paste. Care should be taken to prevent rapid oxidation (or paste slump) and solder bursts caused by violent solvent out-gassing. A typical heating rate is 12C/sec. - Pre-heat/soak: The soak temperature stage serves two purposes; the flux is activated and the board and devices achieve a uniform temperature. The recommended soak condition is: 120-150 seconds at 150C. - Reflow Zone: If the temperature is too high, then devices may be damaged by mechanical stress due to thermal mismatch or there may be problems due to excessive solder oxidation. Excessive time at temperature can enhance the formation of inter-metallic compounds at the lead/board interface and may lead to early mechanical failure of the joint. Reflow must occur prior to the flux being completely driven off. The duration of peak reflow temperature should not exceed 10 seconds. Maximum soldering temperatures should be in the range 215-220C, with a maximum limit of 225C. - Cooling Zone: Steep thermal gradients may give rise to excessive thermal shock. However, rapid cooling promotes a finer grain structure and a more crack-resistant solder joint. The illustration below indicates the recommended soldering profile. Solder Joint Characteristics: Proper operation of this device depends on a reliable void-free attachment of the heatsink to the PWB. The solder joint should be 95% void-free and be a consistent thickness. Rework Considerations: Rework of a device attached to a board is limited to reflow of the solder with a heat gun. The device should not be subjected to more than 225C and reflow solder in the molten state for more than 5 seconds. No more than 2 rework operations should be performed.
Recommended Solder Reflow Profile
240 220 200 183C 180 160 140 DEG (C) 120 100 80 60 40 20 0 0 60 120 TIME (SEC) 180 240 300 1C/SEC SOAK AT 150C FOR 60 SEC 45 SEC (MAX) ABOVE 183C 1C/SEC 10 SEC
7 RMPA1967 Rev. C
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RMPA1967 US-PCS CDMA, CDMA2000-1X and WDCMA Power EdgeTM Power Amplifier Module
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
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DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component is any component of a life 1. Life support devices or systems are devices or support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Rev. I15
8 RMPA1967 Rev. C
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